In semiconductor integrated circuit manufacturing, integrated circuits (ICs) are conventionally tested during manufacturing and prior to shipment to ensure proper operation. Wafer testing is a testing technique commonly used in production testing of wafer-mounted semiconductor ICs where a temporary electrical connection is established between automatic test equipment (ATE) and ICs formed on the wafer to demonstrate proper performance of the ICs. Components used in wafer testing include an ATE test board, a multilayer printed circuit board connected to the ATE which transfers test signals between the ATE, and a probe card assembly. Conventional probe card assemblies include a printed circuit board, a probe head assembly having a plurality of flexible test probes attached thereto, and an interposer electrically connecting the test probes to the printed circuit board. The test probes are conventionally mounted to electrically conductive, typically metallic, bonding pads on a substrate using solder, wire bonding or wedge bonding techniques. In operation, a device under test (DUT) is moved into position so the test probes make contact with corresponding contact points on the DUT.
Along with complexity improvement of circuit designs, rapid development of semiconductor fabrication processes, and demand for circuit performance, ICs have been developed with a three-dimensional (3D) structure to increase circuit performance. Different process techniques can be used in different layers of the 3DIC, and these different chip layers or “dies” are stacked and interconnected using through silicon vias (TSVs).
As 3DICs are formed by a plurality of chip layers having varying process techniques and/or supply voltages on different chips, high-voltage static electricity or noises, commonly referred to as electrostatic discharge (ESD), can pass through the package and/or test equipment. ESD is generally defined as a sudden and momentary electric current that flows between two objects at different electrical potentials. ESD can damage devices fabricated on IC chips causing performance degradation or failures. For example, ESD can damage sensitive components in the 3DIC and test equipment including a ball grid array (BGA) package, control collapse chip connection (C4) package, flip-chip package, pin grid array (PGA) package, and other surface mount packages as well as the test interface, interposer, TSV, metal routing, ubump, gate oxide devices, and other components on the 3DIC.